1. Field of the Invention
The present invention relates generally to photolithographic techniques for forming features in and on semiconductor substrates, and more particularly to a tri-level photolithographic technique for forming regions and structures having very fine geometries, such as very narrow metal lines, on such semiconductor substrates.
The ability to resolve very small features on semiconductor substrates is of increasing importance as more and more devices are placed on individual chips at increasing densities. The use of single-layer photoresist systems to define such small features is often limited since the photoresist must be made relatively thick in order to adequately cover a substrate having an uneven topography. Such thick photoresist layers defy the precise imaging necessary to define very small features because the focus of the exposing radiation will change over the depth of the film. Moreover, radiation that adequately exposes the lower portions of the photoresist may overexpose higher regions formed on top of raised substrate features.
The use of multilayer photoresist systems partially overcomes these problems. A relatively thick layer of an organic polymer (usually referred to as a planarizing or leveling layer) applied over the substrate provides a relatively flat surface. A barrier or image transfer layer is applied over the planarizing layer, followed by an imaging layer over the image transfer layer. The imaging layer is a thin photoresist film which can be imaged to a very high resolution since it avoids the problems associated with uneven exposure and variations in the depth of focus. The pattern is then etched onto the image transfer layer, which may be an oxide, nitride, or organic or inorganic polymer, using the patterned photoresist as a mask. The pattern is ultimately transferred to the planarizing layer by conventional techniques, and the planarizing layer used as a mask for forming the desired features in or on the substrate.
While a substantial improvement over single layer photoresist systems, such tri-level resist systems have not achieved the high level resolution, usually below 1 micron, required for many modern VLSI devices. As recognized by the inventor herein, characteristics of the surface of the image transfer layer render it difficult to apply photoresist imaging layers having a thickness below about 1 micron. As the resolution achieved with a photoresist imaging layer is approximately equal to the thickness of the layer, it can be seen that resolution below 1 micron is not readily achieved.
For these reasons, it would be desirable to provide multilayer photoresist imaging systems capable of providing photolithographic imaging resolutions well below 1 micron. In particular, it would be desirable to provide an improved tri-level photoresist process having an image transfer layer which is sufficiently smooth and free from defects so that very thin imaging layers may be applied thereover.
2. Description of the Background Art
The use of multilayer photoresist imaging systems is described generally in Burgraff, "Multilayer Resist Processing Update," Semiconductor International, August, 1985, pp. 88-92 and "Improved Photoresists for Integrated Circuits Chips Devised," Chemical & Engineering News, Oct. 7, 1985, pp. 27-30.
Tri-level photoresist systems employing a polydimethylsiloxane resin material as the image transfer layer are described in U.S. Pat. No. 4,004,044 and Fried et al. IBM J. Res. Develop. 26:362-371. A similar tri-level photoresist process is described in U.S. Pat. No. 4,493,855, where a siloxane image transfer layer is deposited by plasma polymerization, followed by oven curing. Chou et al. (1985) Appl. Phys. Lett. 46:31-33, describes etching of polysiloxane films in an oxygen plasma.